1. Field of the Invention
The invention relates to a circuit for generating an output sequence of values and to a method and an arrangement for optimizing such a circuit.
2. Description of the Prior Art
Memory components and logic circuits undergo continual improvement. Especially evident is the trend toward increasingly greater memory capacity and faster clock frequencies for memory read and write operations. The manufacture of such chips is extremely expensive and complex. The slightest impurities and other influences during the manufacturing process can cause the chip to later become error-prone or even completely inoperative. For this reason, chips are tested after manufacture, before they are released for actual application. Such tests prescribe that the individual chip memory cells be addressed for write and read operations in a specific sequence or test address pattern. If the operation of the memory cells is error-free, the test leads to the expected results. If the test results deviate, however, this is an indication that a defect exists. Such defects can of course be analyzed to determine their cause.
Which cells are exercised in which order is determined by the aforementioned test address pattern. For high-speed memory components, the individual memory cells should be addressed with the fastest sequence possible. This requires test systems which are capable of issuing consecutive values in the address sequences in the shortest possible time. This requirement for speed has natural limits, which are set by the circuits themselves and the circuit technology.
The fastest technology in today's integrated circuits is based on the gallium arsenide technology, which permits an extremely fast charge carrier movement. In addition, special circuit designs can enable "fast" address sequences to be generated. Circuits that are presently available for generating such fast address sequences are expensive, complex and limited in their capabilities.
It is thus desirable that a simple inexpensive circuit be designed that can interleave a variety of sequences, which means the following: rather than the impossible generation of a fast output sequence of (address) values: EQU C1 C2 C3 C4 C5 etc.
slower partial sequences
______________________________________ C1 C3 C5, etc. and C2 C4 C6 etc. ______________________________________
can be generated and then recombined with a multiplexer into the required fast output sequence: EQU C1; C2; C3; C4; C5; etc.